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data sheet ?2007-2008 cadeka microcircuits llc www.cadeka.com c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a c o m l i n e a r ? CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable a mplif y the human experience features n 0.1db gain fatness to 200mhz n 0.02%/0.01? differential gain/phase n 750mhz -3db bandwidth at g = 2 n 350mhz large signal bandwidth n 1,400v/s slew rate n 4nv/hz input voltage noise n 100ma output current n 20ns enable time n stable for gains of 2v/v or larger n fully specifed at 5v and 5v supplies n CLC1004: pb-free sot23-6 n clc1014: pb-free sot23-5 n clc3004: pb-free soic-16 a pplications n rgb video line drivers n high defnition video driver n video switchers and routers n adc buffer n active flters n cable drivers n imaging applications n radar/communication receivers general description the comlinear CLC1004 (single with disable), clc1014 (single), and clc3004 (triple with disable) are high-performance, voltage feedback am - plifers that provide 750mhz gain of 2 bandwidth, 0.1db gain fatness to 200mhz, and 1,400v/s slew rate. this high performance exceeds the re - quirements of high-defnition television (hdtv) and other multimedia appli - cations. these comlinear high-performance amplifers also provide ample output current to drive multiple video loads. the comlinear CLC1004, clc1014, and clc3004 are designed to operate from 5v or +5v supplies. the CLC1004 and clc3004 offer a fast enable/ disable feature to save power. while disabled, the outputs are in a high- impedance state to allow for multiplexing applications. the combination of high-speed, low-power, and excellent video performance make these ampli - fers well suited for use in many general purpose, high-speed applications including video line driving and imaging applications. typical application - driving multiple video loads ordering information part number package pb-free rohs compliant operating temperature range packaging method CLC1004ist6x sot23-6 yes yes -40c to +85c reel CLC1004ist6 sot23-6 yes yes -40c to +85c rail clc1014ist5x sot23-5 yes yes -40c to +85c reel clc1014ist5 sot23-5 yes yes -40c to +85c rail clc3004iso16x soic-16 yes yes -40c to +85c reel clc3004iso16 soic-16 yes yes -40c to +85c rail moisture sensitivity level for all parts is msl-1. input output a +vs -vs r g r f 75? 75? cable 75? cable 75? cable 75? 75? 75? 75? output b
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 2 CLC1004 pin assignments pin no. pin name description 1 out output 2 -v s negative supply 3 +in positive input 4 -in negative input 5 dis disable pin. enabled if pin is grounded, left foat - ing or pulled below v on , disabled if pin is pulled above v off . 6 +v s positive supply clc3004 pin confguration pin no. pin name description 1 -in1 negative input, channel 1 2 +in1 positive input, channel 1 3 -v s negative supply 4 -in2 negative input, channel 2 5 +in2 positive input, channel 2 6 -v s negative supply 7 -in3 negative input, channel 3 8 +in3 positive input, channel 3 9 -v s negative supply 10 out3 output, channel 3 11 +v s positive supply 12 out2 output, channel 2 13 +v s positive supply 14 dis disable pin. enabled if pin is grounded, left foat - ing or pulled below v on , disabled if pin is pulled above v off . 15 out1 output, channel 1 16 +v s positive supply disable pin truth table pin high low* dis disabled enabled *default open state CLC1004 pin confguration clc3004 pin confguration 2 3 6 4 +in +v s -in 1 -v s out - + 5 dis 2 3 4 13 14 15 16 out1 -vs +vs dis 1 +in1 -in1 5 6 7 -in3 -vs +in2 10 11 12 out2 +vs out3 -in2 +vs 8 +in3 9 -vs
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 3 clc1014 pin assignments pin no. pin name description 1 out output 2 -v s negative supply 3 +in positive input 4 -in negative input 5 +v s positive supply clc1014 pin confguration 2 3 5 4 +in +v s -in 1 -v s out - +
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 4 absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper de - vice function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter min max unit supply voltage 0 14 v input voltage range -v s -0.5v +v s +0.5v v continuous output current 100 ma reliability information parameter min typ max unit junction temperature 150 c storage temperature range -65 150 c lead temperature (soldering, 10s) 260 c package thermal resistance 5-lead sot23 221 c/w 6-lead sot23 177 c/w 16-lead soic 68 c/w notes: package thermal resistance ( q ja ), jdec standard, multi-layer test boards, still air. esd protection product sot23-5 sot23-6 soic-16 human body model (hbm) 2kv 2kv 2kv charged device model (cdm) 1kv 1kv 1kv recommended operating conditions parameter min typ max unit operating temperature range -40 +85 c supply voltage range 4.5 12 v
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 5 electrical characteristics at +5v t a = 25c, v s = +5v, r f = r g =150, r l = 150 to v s /2, g = 2; unless otherwise noted. symbol parameter conditions min typ max units frequency domain response bw ss -3db bandwidth g = +2, v out = 0.2v pp 600 mhz bw ls large signal bandwidth g = +2, v out = 1v pp 400 mhz bw 0.1dbss 0.1db gain flatness g = +2, v out = 0.2v pp 150 mhz bw 0.1dbls 0.1db gain flatness g = +2, v out = 1v pp 120 mhz time domain response t r , t f rise and fall time v out = 1v step; (10% to 90%) 1.2 ns t s settling time to 0.1% v out = 1v step 10 ns os overshoot v out = 0.2v step 2 % sr slew rate 1v step 750 v/s distortion/noise response hd2 2nd harmonic distortion v out = 1v pp , 5mhz -72 dbc hd3 3rd harmonic distortion v out = 1v pp , 5mhz -85 dbc thd total harmonic distortion v out = 1v pp , 5mhz 70 db d g differential gain ntsc (3.58mhz), ac-coupled, r l = 150 0.08 % d p differential phase ntsc (3.58mhz), ac-coupled, r l = 150 0.04 ip3 third order intercept v out = 1v pp , 10mhz 38 dbm sfdr spurious free dynamic range v out = 1v pp , 5mhz 63 dbc e n input voltage noise > 1mhz 4 nv/hz i n input current noise > 1mhz 4 pa/hz x talk crosstalk channel-to-channel 5mhz, v out = 1v pp 70 db dc performance v io input offset voltage 0 mv dv io average drift 4 v/c i b input bias current 3.2 a di b average drift 20 na/c psrr power supply rejection ratio dc 56 db a ol open-loop gain v out = v s / 2 65 db i s supply current per channel 11 ma disable characteristics t on turn on time 20 ns t off turn off time 40 ns off ios off isolation 5mhz -78 db v off power down input voltage dis pin, disabled if pin is pulled above v off = v s - 2v disabled if > (v s - 2v) v v on enable input voltage dis pin, enabled if pin is grouned, left open, or pulled below v on = v s - 4v enabled if < (v s - 4v) v i sd disable supply current CLC1004; dis pin is pulled to v s 0.4 ma clc3004; dis pin is pulled to v s 0.4 ma input characteristics r in input resistance non-inverting 4.5 m c in input capacitance 1.0 pf cmir common mode input range 1.5 to 3.5 v cmrr common mode rejection ratio dc 50 db
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 6 electrical characteristics at +5v continued t a = 25c, v s = +5v, r f = r g =150, r l = 150 to v s /2, g = 2; unless otherwise noted. symbol parameter conditions min typ max units output characteristics r o output resistance closed loop, dc 0.1 v out output voltage swing r l = 150 1.5 to 3.5 v i out output current 100 ma notes: 1. 100% tested at 25c
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 7 electrical characteristics at 5v t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. symbol parameter conditions min typ max units frequency domain response bw ss -3db bandwidth g = +2, v out = 0.2v pp 750 mhz bw ls large signal bandwidth g = +2, v out = 2v pp 350 mhz bw 0.1dbss 0.1db gain flatness g = +2, v out = 0.2v pp 200 mhz bw 0.1dbls 0.1db gain flatness g = +2, v out = 2v pp 120 mhz time domain response t r , t f rise and fall time v out = 2v step; (10% to 90%) 1.3 ns t s settling time to 0.1% v out = 2v step 10 ns os overshoot v out = 0.2v step 1.5 % sr slew rate 2v step 1400 v/s distortion/noise response hd2 2nd harmonic distortion v out = 2v pp , 5mhz -71 dbc hd3 3rd harmonic distortion v out = 2v pp , 5mhz -82 dbc thd total harmonic distortion v out = 2v pp , 5mhz 70 db d g differential gain ntsc (3.58mhz), ac-coupled, r l = 150 0.02 % d p differential phase ntsc (3.58mhz), ac-coupled, r l = 150 0.01 ip3 third order intercept v out = 2v pp , 10mhz 41 dbm sfdr spurious free dynamic range v out = 1v pp , 5mhz 65 dbc e n input voltage noise > 1mhz 4 nv/hz i n input current noise > 1mhz 4 pa/hz x talk crosstalk channel-to-channel 5mhz, v out = 2v pp 70 db dc performance v io input offset voltage (1) -10 0 10 mv dv io average drift 4 v/c i b input bias current (1) -20 3.2 20 a di b average drift 20 na/c psrr power supply rejection ratio (1) dc 40 56 db a ol open-loop gain v out = v s / 2 70 db i s supply current (1) per channel 12 17 ma disable characteristics t on turn on time 20 ns t off turn off time 40 ns off ios off isolation 5mhz -78 db v off power down input voltage dis pin, disabled if pin is pulled above v off = v s - 1v disabled if > (v s - 1v) v v on enable input voltage dis pin, enabled if pin is grouned, left open, or pulled below v on = v s - 2v enabled if < (v s - 2v) v i sd disable supply current (1) CLC1004; dis pin is pulled to v s 0.4 0.8 ma clc3004; dis pin is pulled to v s 0.4 0.9 ma input characteristics r in input resistance non-inverting 4.5 m c in input capacitance 1.0 pf cmir common mode input range 3.2 v cmrr common mode rejection ratio (1) dc 40 60 db
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 8 electrical characteristics at 5v continued t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. symbol parameter conditions min typ max units output characteristics r o output resistance closed loop, dc 0.1 v out output voltage swing r l = 150 (1) 3.0 3.8 v i out output current 220 ma notes: 1. 100% tested at 25c
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 9 typical performance characteristics t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. frequency response vs. v out frequency response vs. temperature frequency response vs. c l frequency response vs. r l non-inverting frequency response inverting frequency response - 9 - 6 - 3 0 3 6 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) g = 2 g = 5 g = 1 0 v ou t = 0.2v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) g = - 1 g = - 2 g = - 5 g = - 10 v ou t = 0.2v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) c l = 1000pf r s = 3.3 c l = 500pf r s = 5 c l = 100pf r s = 10 c l = 50pf r s = 15 c l = 20pf r s = 20 v out = 0.2v pp - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) r l = 500 v ou t = 0.2v pp r l = 1k r l = 100 r l = 50 r l = 25 - 9 - 6 - 3 0 3 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) v ou t = 1v pp v ou t = 2v pp v ou t = 4v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 0.1 1 10 100 1000 10000 normalized gain (db) frequency (mhz) + 85degc - 40degc + 25degc v ou t = 0.2v pp
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 10 typical performance characteristics t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. frequency response vs. v out at v s = 5v frequency response vs. temperature at v s = 5v frequency response vs. c l at v s = 5v frequency response vs. r l at v s = 5v non-inverting frequency response at v s = 5v inverting frequency response at v s = 5v - 9 - 6 - 3 0 3 6 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) g = 2 g = 5 g = 1 0 v ou t = 0.2v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) g = - 1 g = - 2 g = - 5 g = - 10 v ou t = 0.2v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) c l = 1000pf r s = 3.3 c l = 500pf r s = 5 c l = 100pf r s = 10 c l = 50pf r s = 15 c l = 20pf r s = 20 v out = 0.2v pp - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) r l = 500 v ou t = 0.2v pp r l = 1k r l = 100 r l = 50 r l = 25 - 9 - 6 - 3 0 3 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) v ou t = 1v pp v ou t = 2v pp v ou t = 2.5v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 0.1 1 10 100 1000 10000 normalized gain (db) frequency (mhz) + 85degc - 40degc + 25degc v ou t = .2v pp
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 11 typical performance characteristics - continued t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. closed loop output impedance vs. frequency input voltage noise -3db bandwidth vs. v out -3db bandwidth vs. v out at v s = 5v gain flatness gain flatness at v s = 5v - 1.2 - 1 - 0.8 - 0.6 - 0.4 - 0.2 0 0.2 0.4 0.6 0.8 1 1.2 0.1 1 10 100 normalized gain (db) frequency (mhz) v out = 2v pp - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) v out = 2v pp 150 250 350 450 550 650 750 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 - 3db bandwidth (mhz) v out (v pp ) 100 200 300 400 500 600 0.0 0.5 1.0 1.5 2.0 2.5 - 3db bandwidth (mhz) v out (v pp ) output resistance (?) frequency (hz) 10k 100k 1m 10m 100m 1g 0.01 0.1 1 10 v s = 5.0v input voltage noise (nv/hz) frequency (mhz) 0.0001 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 12 typical performance characteristics - continued t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. cmrr vs. frequency psrr vs. frequency 2nd harmonic distortion vs. v out 3rd harmonic distortion vs. v out 2nd harmonic distortion vs. r l 3rd harmonic distortion vs. r l - 100 - 90 - 80 - 70 - 60 - 50 - 40 0 5 10 15 20 distortion (dbc) frequency (mhz) r l = 150 v ou t = 2v pp r l = 499 - 100 - 90 - 80 - 70 - 60 - 50 0 5 10 15 20 distortion (dbc) frequency (mhz) r l = 150 v ou t = 2v pp r l = 499 - 100 - 90 - 80 - 70 - 60 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 distortion (dbc) output amplitude (v pp ) 10mhz 5mhz 1mhz - 100 - 90 - 80 - 70 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 distortion (dbc) output amplitude (v pp ) 10mhz 5mhz 1mhz cmrr (db) frequency (hz) 10k 100k 1m 10m 100m -55 -50 -45 -40 -35 -30 -25 -20 v s = 5.0v psrr (db) frequency (mhz) 0.01 0.1 1 10 100 -70 -60 -50 -40 -30 -20 -10 0
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 13 typical performance characteristics - continued t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. differential gain & phase ac coupled output differential gain & phase dc coupled output large signal pulse response large signal pulse response at v s = 5v small signal pulse response small signal pulse response at v s = 5v - 0.150 - 0.100 - 0.050 0.000 0.050 0.100 0.150 0 20 40 60 80 100 voltage (v) t i m e ( n s ) 2.35 2.40 2.45 2.50 2.55 2.60 2.65 0 20 40 60 80 100 voltage (v) t i m e ( n s ) - 3 - 2 - 1 0 1 2 3 0 20 40 60 80 100 voltage (v) t i m e ( n s ) 1 1.5 2 2.5 3 3.5 4 0 20 40 60 80 100 voltage (v) t i m e ( n s ) - 0.04 - 0.03 - 0.02 - 0.01 0 0.01 0.02 0.03 - 0 . 7 - 0.5 - 0.3 - 0.1 0.1 0.3 0.5 0 . 7 diff gain (%) and diff phase ( ) i n p u t v o l t a g e ( v ) dg r l = 150 ac coupled dp - 0.04 - 0.03 - 0.02 - 0.01 0 0.01 0.02 0.03 0.04 - 0 . 7 - 0.5 - 0.3 - 0.1 0.1 0.3 0.5 0 . 7 diff gain (%) and diff phase ( ) i n p u t v o l t a g e ( v ) dg r l = 150 dc coupled dp
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 14 typical performance characteristics - continued t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. differential gain & phase ac coupled output at v s = 2.5v differential gain & phase dc coupled at v s = 2.5v - 0.2 - 0.15 - 0.1 - 0.05 0 0.05 0.1 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 0.3 0.4 diff gain (%) and diff phase ( ) i n p u t v o l t a g e ( v ) dg r l = 150 ac coupled dp - 0.3 - 0.25 - 0.2 - 0.15 - 0.1 - 0.05 0 0.05 0.1 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 0.3 0.4 diff gain (%) and diff phase ( ) i n p u t v o l t a g e ( v ) dg r l = 150 dc coupled dp
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 15 application information basic operation figures 1 and 2 illustrate typical circuit confgurations for non-inverting, inverting, and unity gain topologies for dual supply applications. they show the recommended bypass capacitor values and overall closed loop gain equations. + - r f 0.1f 6.8f output g = 1 + ( r f /r g ) input +v s -v s r g 0.1f 6.8f r l figure 1. typical non-inverting gain circuit figure 2. typical inverting gain circuit power dissipation power dissipation should not be a factor when operating under the stated 1000 ohm load condition. however, ap - plications with low impedance, dc coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond its intended operat - ing range. maximum power levels are set by the absolute maximum junction rating of 150c. to calculate the junction tem - perature, the package thermal resistance value theta ja (? ja ) is used along with the total die power dissipation. t junction = t ambient + (? ja p d ) where t ambient is the temperature of the working environment. in order to determine p d , the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. p d = p supply - p load supply power is calculated by the standard power equa - tion. p supply = v supply i rms supply v supply = v s+ - v s- power delivered to a purely resistive load is: p load = ((v load ) rms 2 )/rload eff the effective load resistor (rload eff ) will need to include the effect of the feedback network. for instance, rload eff in fgure 3 would be calculated as: r l || (r f + r g ) these measurements are basic and are relatively easy to perform with standard lab equipment. for design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. here, p d can be found from p d = p quiescent + p dynamic - p load quiescent power can be derived from the specifed i s val - ues along with known supply voltage, v supply . load power can be calculated as above with the desired signal ampli - tudes using: (v load ) rms = v peak / 2 ( i load ) rms = ( v load ) rms / rload eff the dynamic power is focused primarily within the output stage driving the load. this value can be calculated as: p dynamic = (v s+ - v load ) rms ( i load ) rms assuming the load is referenced in the middle of the pow - er rails or v supply /2. figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the pack - ages available. + - r f 0.1f 6.8f output g = - ( r f /r g ) for optimum input offset voltage set r 1 = r f || r g input +v s -v s 0.1f 6.8f r l r g r 1
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 16 0 0.5 1 1.5 2 2.5 - 40 - 20 0 20 40 60 80 maximum power dissipation (w) ambient temperature ( c) sot23 - 6 sot23 - 5 soic - 16 figure 3. maximum power derating driving capacitive loads increased phase delay at the output due to capacitive load - ing can cause ringing, peaking in the frequency response, and possible unstable behavior. use a series resistance, r s , between the amplifer and the load to help improve stability and settling performance. refer to figure 4. + - r f input output r g r s c l r l figure 4. addition of r s for driving capacitive loads table 1 provides the recommended r s for various capaci - tive loads. the recommended r s values result in <=1db peaking in the frequency response. the frequency re - sponse vs. c l plots, on page 7, illustrates the response of the clcx004. c l (pf) r s () -3db bw (mhz) 20 20 400 50 15 270 100 10 195 500 5 80 1000 3.3 58 table 1: recommended r s vs. c l for a given load capacitance, adjust r s to optimize the tradeoff between settling time and bandwidth. in general, reducing r s will increase bandwidth at the expense of ad - ditional overshoot and ringing. overdrive recovery an overdrive condition is defned as the point when ei - ther one of the inputs or the output exceed their specifed voltage range. overdrive recovery is the time needed for the amplifer to return to its normal or linear operating point. the recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. the clcx004 will typically recover in less than 20ns from an overdrive condition. figure 5 shows the CLC1004 in an overdriven condition. figure 5. overdrive recovery layout considerations general layout and supply bypassing play major roles in high frequency performance. c adeka has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. follow the steps below as a basis for high frequency layout: ? include 6.8f and 0.1f ceramic capacitors for power supply decoupling ? place the 6.8f capacitor within 0.75 inches of the power pin ? place the 0.1f capacitor within 0.1 inches of the power pin ? remove the ground plane under and around the part, especially near the input and output pins to reduce para - sitic capacitance ? minimize all trace lengths to reduce series inductances refer to the evaluation board layouts below for more in - formation. - 3 - 2 - 1 0 1 2 3 - 3 - 2 - 1 0 1 2 3 0 20 40 60 80 100 120 140 160 180 200 output voltage (v) input voltage (v) t i m e ( n s ) output input v in = 2.5v pp g = 5
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 17 evaluation board information the following evaluation boards are available to aid in the testing and layout of these devices: evaluation board # products ceb002 CLC1004, clc1014 ceb012 clc3004 evaluation board schematics evaluation board schematics and layouts are shown in fig - ures 9-14. these evaluation boards are built for dual- sup - ply operation. follow these steps to use the board in a single-supply application: 1. short -vs to ground. 2. use c3 and c4, if the -v s pin of the amplifer is not directly connected to the ground plane. figure 9. ceb002 schematic figure 10. ceb002 top view figure 11. ceb002 bottom view
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 18 rout1 rf1 rin1 rg1 in1 out1 board mounting holes rout3 rf3 rin3 rg3 in3 out3 rout2 rf2 rin2 rg2 in2 out2 dis 14 14 14 15 1 2 12 4 5 3,6,9 16,13,11 10 7 8 figure 12. ceb012 schematic figure 13. ceb012 top view figure 14. ceb012 bottom view
data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a ?2007-2008 cadeka microcircuits llc www.cadeka.com 19 mechanical dimensions sot23-5 package sot23-6 package
for additional information regarding our products, please visit cadeka at: cadeka.com cadeka, the cadeka logo design, comlinear, the comlinear logo design, and arctic are trademarks or registered trademarks of cadeka microcircuits llc. all other brand and product names may be trademarks of their respective companies. cadeka reserves the right to make changes to any products and services herein at any time without notice. cadeka does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by cadeka; nor does the purchase, lease, or use of a product or service from cadeka convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of cadeka or of third parties. copyright ?2007-2008 by cadeka microcircuits llc. all rights reserved. cadeka headquarters loveland, colorado t: 970.663.5452 t: 877.663.5452 (toll free) data sheet c o m l i n e a r CLC1004, clc1014, clc3004 single and triple, 750mhz amplifers with disable rev 1a a mplif y the human experience mechanical dimensions soic-16 package

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